1. Field of the Invention
This invention generally relates to integrated circuit (IC) and liquid crystal display (LCD) fabrication and, more particularly, to a display with pixel elements controlled using a dual-gate thin-film transistor (DG-TFT).
2. Description of the Related Art
In order to achieve high contrast and minimize crosstalk in a display system, such as a liquid display or a light-emitting diode panel, it is important to employ an active matrix (AM) architecture, where one or more active devices are used in each pixel to control the pixel switching characteristics. Various AM architectures exist, varying in complexity and principles of operation. Generally, a tradeoff exists between switching speed (fast refresh times) and storage time (low current leakage). Greater pixel functionality can be obtained by using a greater number of active elements to control the pixel. Of course, since the dimensions of the pixel are fixed, the number of thin-film transistors (TFTs) that can be incorporated into each pixel cannot be arbitrarily large. As soon as a pixel architecture is implemented, the switching characteristics of the pixel (i.e. how fast it can charge/discharge to the new voltage/current values as the picture is refreshed) are considered fixed.
FIG. 13 is a schematic drawing depicting two examples of conventional active matrix system pixels (prior art). In many embodiments, the display is built on a temperature-sensitive substrate, such as glass, necessitating the use of amorphous-Si or polycrystalline Si TFTs formed at low temperature. When enabled in the ON state, the switching TFT activates a constant current (or voltage) source that controls the liquid crystal or light emitting element (left schematic). A simplified representation is shown to the right, where the source/light element combination is replaced by an equivalent load impedance ZL.
FIG. 14 is a schematic depicting a conventional LCD display pixel architecture, employing amorphous-Si or low-temperature polycrystalline silicon N-channel TFTs (prior art). Vdata is the data (column) line, Vr1 and Vr2 are two consecutive row selection lines, CS is the storage capacitor, CLC is the liquid crystal (LC) element (a light valve), and VC the potential across the LC, which determines the light intensity of that specific pixel.
FIG. 15 is a signal diagram for the circuit of FIG. 14 (prior art). A typical running sequence for this pixel, not including parasitic effects (such as the parasitic gate-source capacitance of the TFT), is shown. Assume that the Vr2 line (the row line for the next row of pixels) is de-activated, i.e. at a negative voltage. When Vr1 switches ON (positive voltage), the switching transistor turns ON. The voltage level present at Vdata then propagates through the TFT and charges the storage capacitor Cs and the liquid crystal element capacitance (CLC). The time it takes to store this value is indicated by trise in the plot of output voltage VC. trise is a function of the channel resistance of the TFT, itself a function of mobility and threshold voltage, and the charging capacitors CS and CLC.
After the capacitors have charged, Vr1 turns OFF (i.e. negative), and the TFT turns OFF. Ideally, the programmed value VC should stay constant. However, the voltage changes slightly because of leakage through the TFT. The TFT has a finite channel resistance in its OFF state. This leakage is indicated by Vleak in the plot of VC. The brightness of the pixel is controlled by VC, so Vleak is minimized to prevent changes in an image with respect to time. When a pixel is to be programmed again (a negative value of Vdata), Vr1 turns on again, and the charging-retaining process described above is repeated.
FIG. 16 is a schematic drawing of a conventional LED pixel architecture (prior art). In the case of a light-emitting diode active matrix display, an individual LED is built in each pixel. The depicted pixel architecture employs PMOS TFTs.
Here, a constant power supply line (VDD) is required for all pixels. The timing diagram would be similar to that of the LCD pixel (FIG. 15). When Vr1 turns ON, TFT M1 turns ON, causing the value in Vdata to be stored in storage capacitor CS. This capacitor is across the gate-source terminals of M2, which then acts a constant current supply for the LED. When Vr1 turns OFF, M1 turns OFF, and the charge stored in Cs continues to induce a constant current through the LED via M2.
As with the LCD pixel, there is a rise time associated with the charging of CS through M1, determined partly by the threshold voltage of M1, as well as a loss in the programmed voltage across Cs due to leakage through M1, when M1 is OFF.
FIG. 17 is a schematic diagram of a conventional active-matrix system (prior art). Pixel data is loaded in parallel (i.e. simultaneously in all columns). The row in which the Data is stored is determined by the currently-on Row (in this case Row2). In the next time instance, Row2 will be off, Row3 will be on, and a new set of Data will be present.
It would be advantageous if the both the switching time and leakage current of a display pixel element could be improved without increasing the number of TFT's associated with the pixel.